This invention relates generally to embedded processors. More particularly, this invention relates to a technique for identifying a scratch pad memory configuration associated with an embedded processor.
An embedded processor is an electronic control and computation device incorporated into an engineered system, such as a camera, game console, printer, personal digital assistant, and the like. An embedded processor has a processor core and an associated memory. The associated memory commonly includes a scratch pad memory, which is a general-purpose random access memory region for the processor core. The patent application entitled xe2x80x9cScratch Pad RAM with Cache-Like Access Timesxe2x80x9d, Ser. No. 09/494,488, filed Jan. 31, 2000, and assigned to the assignee of the present invention, describes a technique for accessing scratch pad memory. The contents of the application are incorporated herein. The memory associated with a processor core may also include an instruction cache, a data cache, main memory and I/O devices.
The processor core realizes a number of benefits by using the scratch pad memory instead of the data cache. For example, stores to the scratch pad memory are not written to main memory. For local data, this reduces the bus bandwidth associated with store traffic. Advantageously, a scratch pad data array can be relatively large compared to a cache way. In addition, a full tag array is not needed for scratch pad memory. The equivalent tag functionality is normally replaced by a simple decode of the physical address to determine hit or miss.
Embedded processors are highly customized devices. While a processor core may be common to many embedded processors, other components associated with the processor core, such as scratch pad memory, typically have unique configurations. These unique configurations lead to problems in debugging embedded processor systems.
There are commercially available tools to debug embedded systems. A limitation associated with these tools is that they require information on the configuration of the embedded processor. Thus, a configuration file must be supplied to the tool. The problem with this approach is that someone must generate a configuration file and the tool vendor must support the configuration file. This requires additional work by the system designer and the tool vendor. In addition, the system designer and the tool vendor need to coordinate their work to insure interoperability.
In view of the foregoing, it would be highly desirable to provide an automated technique for identifying a scratch pad memory configuration. The technique should operate through general interrogation of an embedded processor and provide scratch pad configuration information that is readily usable by a debugging tool.
The invention includes an embedded processor with a processor core and scratch pad memory connected to the processor core. The scratch pad memory includes a set of scratch pad regions. The scratch pad memory stores values characterizing base addresses and region sizes of the set of scratch pad regions.
The invention also includes a processor probe. The processor probe has input/output circuitry and control logic connected to the input/output circuitry. A scratch pad configuration query module is connected to the control logic. The scratch pad configuration query module is configured to initiate, in conjunction with the control logic and the input/output circuitry, access to a scratch pad memory of an embedded processor. The scratch pad memory includes a set of scratch pad regions. The scratch pad configuration query module initiates a read of values characterizing addresses and region sizes for scratch pad regions of the set of scratch pad regions.
The invention also includes a host computer with input/output circuitry operative to interface with an embedded processor. A central processing unit is connected to the input/output circuitry. A memory is connected to the central processing unit. The memory stores a scratch pad configuration query module configured to initiate, in conjunction with the central processing unit and the input/output circuitry, access to a scratch pad memory associated with the embedded processor. The scratch pad memory includes a set of scratch pad regions. The scratch pad configuration query module initiates a read of values characterizing addresses and region sizes for scratch pad regions of the set of scratch pad regions.
The invention further includes a computer readable medium with a scratch pad configuration query module with executable instructions to initiate access to an embedded processor with a scratch pad memory including a set of scratch pad regions. The scratch pad configuration query module initiates a read of values characterizing addresses and region sizes for scratch pad regions of the set of scratch pad regions.
Another aspect of the invention is a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configuration of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the configuration file.
The invention provides an automated mechanism for identifying the location and size of an arbitrary number of regions within a scratch pad memory. The invention utilizes a general interrogation technique to provide scratch pad configuration information that can be used by the debugging tool. Advantageously, the invention allows the debugging tool access to the scratch pad without modification to the debugging tool and without modification to the communications protocol between the debugging tool and a processor probe, such as an EJTAG probe.